Andrew Young

Results 13 issues of Andrew Young

Running the following test with `firtool test.fir`: ``` circuit Top: extmodule Other: input a: UInt module Top: inst x of Other inst y of Other y.a

FIRRTL

Inspired by the PR to print IR after specific passes, I thought people might also be interested in this patch I use sometimes for debugging. This adds an experimental pass...

FIRRTL

`CreateSiFiveMetadata` will not emit information about modules annotated with `SignalMappingAnnotation`. https://github.com/llvm/circt/blob/2e87750c597abe0a12c5b94cb00f441159203e17/lib/Dialect/FIRRTL/Transforms/CreateSiFiveMetadata.cpp#L332 This might have been copied from the original pass implementation. This annotation might not ever actually appear in the...

FIRRTL

I am mostly curious if this is what is supposed to happen, and there doesn't appear to be any tests of this behavior. A don't touch on an instance's port...

FIRRTL

From: https://github.com/llvm/circt/pull/3351#issue-1271452116 In addition to these changes, I noticed that the two pictures in the folded-vs-unfolded-modules table (at the bottom of [this section](https://circt.llvm.org/docs/FIRRTLAnnotations/#targets)) aren't displaying on the website. I'm not...

documentation
FIRRTL

### Checklist - [x] Did you specify the current behavior? - [x] Did you specify the expected behavior? - [x] Did you provide a code example showing the problem? -...

A long time ago, HW module op would store its inputs and outputs using a function type. This lacked the ability to intermix input and output ports the way verilog...

HW

Read Eval Print Loop

Using OMR::VirtualMachineOperandStack does not change the way which methods are called. It can be enabled or disabled separately from the calling styles.

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