Andrew Young

There was a strong preference by developers to use the name of the signal, so I think this is the way to go. Maybe we should bring this up at...

@zyedidia you can rebase the PR

Are you seeing this issue in the wild somehow, or is there a test we can add? It [looks](https://github.com/llvm/circt/blob/main/lib/Dialect/FIRRTL/Import/FIRLexer.cpp#L162) like the `curBuffer` is always the main bufffer. Could you elaborate...

would be good to have some parser (parse-basic.fir) and flow checking tests (connect-errors.mlir).

@zyedidia The flow checking is implemented as a verifier that is run after each pass. In this case, it is failing after the `LowerCHIRRTL` pass. It attaches the `bits` operation...

During expand whens, if we form a mux with invalid and another value, we choose the other value. E.g. `mux(p, v, invalid) => v`. We found that if we apply...

From an offline message, @seldridge notes that this code path doesn't get exercised in practice because the Instance op annotations are moved onto the Module as non-local annotations: ``` circuit...

There is a similar test in the verilog parser suite: https://chipsalliance.github.io/sv-tests-results/?v=verilator+9.2.1+initial

This should be handled by combinational loop detection. SFC produces: ``` Exception in thread "main" firrtl.transforms.CheckCombLoops$CombLoopException: : [module Top] Combinational loop detected: Top.x.a Top.y.a Top.x.a ``` --- A slightly smaller...

I copied the std::vector solution in https://github.com/llvm/circt/pull/3390, but I think we should leave this issue open to track down what is actually going on and see if we can find...