Catherine

> it is then the task of the code that does use `Instance` to properly handle the `EnableSignal()`. Ah I see, so your complaint isn't that the code that uses...

> I prefer solution that does this by default nMigen has no idea which ports of the instance are clocks, resets, or enables, nor does it have any idea that...

Sure, I'm fine with adding `EnableSignal` in principle, even though it's a bit of a strange addition. The problem can be better illustrated with a reset. You're concerned about a...

I see. Do I understand it correctly that you're suggesting that `EnableInserter` look for `EnableSignal()`, and if it can't find one, insert a clock gating primitive?

There are a few issues here. First, many FPGAs do not have a clock gating primitive. What should iCE40 do here, for example? There is no vendor-sanctioned way to gate...

> I do think yosys needs to be extended to handle the clock gating primitive and the primitive does not necessarily have to translate directly to a real physical cell...

> For users they should behave as other nmigen block including `EnableInserter` functionality. But you don't need a core primitive that automatically introduces clock gating to make such instances work...

I think adding `EnableSignal` is reasonable and I will do so. A good approach for implementing it would be to ditch fragment transformation completely as a concept; instead of mutating...

@Fatsie By the way, I especially like your suggestion of adding `EnableSignal` because, as it turns out, `EnableInserter` already has something very much like it, but as an ad-hoc transformation...

I'm rewriting the simulator right now so that it would not need the (expensive) memory lowering. So I'll keep this open, with the understanding that `Memory.simulate` will go away completely.