Catherine
Catherine
I wouldn't be the one to implement this. I would accept a PR implementing this though.
@sbourdeauducq Here's the major obstacle to getting this done: instance ports. Inout and in ports can in principle be ignored (though that raises the question of whether we're going for...
Reduced testcase: ```python from nmigen import * from nmigen.build import * from nmigen.vendor.xilinx_7series import * class se(Elaboratable): def __init__(self, p): self.p = p def elaborate(self, platform): m = Module() m.submodules.obuf...
By the way, why are you adding a "fake clock"? It's not necessary to have a default clock unless your code explicitly relies on it, you just need to make...
Ah, yeah. Documentation for that needs to be improved.
I'll fix this, but this might require a fairly significant redesign of use-def tracking (to make it per-bit rather than per-signal), so the fix is unlikely to be quick.
You're welcome! That sounds like many of my goals when making nMigen have been achieved.
The most idiomatic way to do this is to make the `Array` associative, and make sure that initializing it with a list uses consecutive indices. (The indices still all have...
This is a self-contained feature that doesn't have backwards compatibility concerns, so it doesn't have to be in 0.1.
How would it be presented to the user?