Catherine
Catherine
One thing to add is that for a while I wanted to add some first-class interface for specifying port *directions*, essentially the same thing as describing something as `Signal(8), in`...
My proposal for the stream interface is to use four signals: `data`, `ack` (aka `tready` in AXI4), `stb` (aka `tvalid` in AXI4), and `eop` (aka `tlast` in AXI4), all with...
We can make `ack`, `rdy` and `eop` be `Signal(reset=1)`, that should do the trick.
I don't think this is relevant to Wishbone, since it does not have a streaming interface.
I believe that an implementation of [Rigel](http://graphics.stanford.edu/papers/rigel/rigel-low.pdf) would provide every single feature @jordens requested.
AsyncFIFO currently doesn't support non-power-of-2 memories anyway so it has no illegal states. And I'm not sure if it's possible to support such memories while still using a Gray counter.
> How would the write half discard the data in the FIFO though (with minimal side effects)? CDC ping-pong with a "clear-request plus acknowledge" to the read side? I've thought...
@programmerjake You are (unfortunately, for this approach) completely correct. I will need to find a different one.
> I would think that most SRAMs don't get reset on ASICs either, so that shouldn't interfere with BRAM inference. The problem isn't that the SRAM itself gets reset, but...