Catherine comments

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                                            Catherine

class Memory: add reset_less parameter that will not initialize memories with 0 value in generated RTL.

> But the `reset_less` parameter is now already introducing non-determinism in the design. You don't know what value the signal has when the reset comes and it will retain that...

class Memory: add reset_less parameter that will not initialize memories with 0 value in generated RTL.

> The reset can come at any time so the signal can have any value when the reset comes. With `reset_less` `True` the value won't be changed by the clock...

class Memory: add reset_less parameter that will not initialize memories with 0 value in generated RTL.

> Robust in what way ? Do you mean the difference in behavior of pysim handling of unitialized values and 'X'/'U' propogation in different simulators ? For example verilator is...

class Memory: add reset_less parameter that will not initialize memories with 0 value in generated RTL.

> Is it the same for 'U', e.g. unitialized ? Neither Yosys nor Verilog have `U`, only `X`. VHDL does have both `X` and `U`; I did not investigate this...

class Memory: add reset_less parameter that will not initialize memories with 0 value in generated RTL.

> then aren't there better tools to prove that from formal verification? AFAIK, right now SymbiYosys does not model `X`. So nMigen would have to emit special code to handle...

class Memory: add reset_less parameter that will not initialize memories with 0 value in generated RTL.

> There may be no need for x or u at all if all you want is to prove that the actual value 0 or 1 does not matter (in...

Implement a sanitizer for memory port combinations

# Lattice iCE40 ## DRAM No distributed RAM. ## BRAM Configurable as 2048x2, 1024x4, 512x8 or 256x16. Block RAM rules: * Port A: read-only. * Port B: write-only. * All...

Implement a sanitizer for memory port combinations

@nakengelhardt Can you explain why does UG473 specify the BRAM dimensions for SDP mode specifically? Is it different for TDP mode?

Add a nmigen example

Please send the PR against the nmigen/nmigen-boards repo instead.

hdl.ast.Value.word_select() works incorrectly on actual platform (ECP5 Versa)

Interesting. It could be a bit width issue. Could you try to reproduce this by simulating in iverilog?