Catherine
Catherine
> If simulation supports multiple clock domains (it should) then there is nothing really special about it, I think? There is if there are two clock domains defined to be...
> and I think they should not be allowed: a synchronous process must be associated with a single clock signal and a single sensitivity edge Among other things this restriction...
> Currently generated RTL by nmigen initializes memories by default with 0, which does not match behavior of a memory on an ASIC. This is true. However, nMigen initializes signals...
> Difference is that for registers (asynchronous) reset flipflops will be used and get thus the right value using the reset. This is not the case for memories. But unlike...
> Actually it's introducing back a feature from Migen where RTL generation actually was made altered for ASIC. That feature was removed from Migen because it was thought that no...
> * reset_less synchronous signals are not initialized in the initial section of generated RTL code independent of platform. To me setting `reset_less` to `True` indicates that one does not...
> Can you give also example of code that actually depends on the fact that value is set at POR but not at clock domain reset ? Any FPGA design...
> Bugger, due to lack of good documentation this was not clear to me up to now. It is documented in the docstring for `Signal`, at least in nMigen: https://github.com/m-labs/nmigen/blob/834fe3c700e420586b7c299bd42d2417966fa1c2/nmigen/hdl/ast.py#L809-L812...
> An ASIC designer like me sees POR also as reset logic; so '_no reset logic for this `Signal` in synchronous statements_' I interprete than also as no init during...
> I agree that also implementing unitialized value support in pysim would be the best solution but this would have a performance impact. I propose using a special value `Uninitialized`...