Vitor Antunes

I'm open to improvement suggestions, so let's keep this open. Free time is not much lately, but I'll take this into account while fixing the bug you uncovered. Are you...

Hi Antoine, I have a Vim function that does something similar to what you accomplish with your plugin, although mine is much simpler and would not support multiple ports per...

More examples. In the following scenarios `my_function()` has one extra indentation level: ``` SystemVerilog assign test = { 3'b0 , `ifdef SOMETHING 1'b1 `else 1'b0 `endif }; my_function(); ``` or:...

Hi Keshava, What kind of demo would you be looking for? Most of the information available on this plugin is in its [README.md](https://github.com/vhda/verilog_systemverilog.vim/blob/master/README.md) and the included Vim help text (`:help...

Automatic tests are failing and looking at your change I don't think it does what you want. Please try the suggestion I made. You can run the tests on your...

Just noticed your problem is with matchit. This is the file you're looking for https://github.com/vhda/verilog_systemverilog.vim/blob/master/ftplugin/verilog_systemverilog.vim

Hi Tianrui, Sorry for the late reply, but I missed this request. Unfortunately, free time has not been abundant, so I've not worked on that development. Thanks for understanding, Vitor

Let me leave this open as a reminder.

Hi Jim, Universal Ctags should support `typedef struct`, but I don't think I've added support for simple `struct` declarations. Would you be so kind and include an example here? Thanks,...

I think you are not using the required arguments when generating the tags file. Please take a look at the omni completion section in the readme and help documentation, update...