Vitor Antunes

I'm using the development version of ctags, but this is Verilog, not Python, and I still did not implement signature extraction in that parser. The problem is that the change...

Did you have time to think about this request? If you're worried about the impact of this change, I don't mind if this functionality requires a global variable to be...

This is mostly useful in vim, where you don't have access to the extra attributes of the tags. So if you want to search for the contents of, let's say,...

We can always do a small check for the presence of that file, it wouldn't slow down the runtime that much.

I can't find a way of disabling this highlight on my side, as it is. I've looked at some of those rainbow plugins and some have an "after" option that...

Such indentation could always be disabled using `g:verilog_disable_indent_lst`. All indentations are increments of the current level. That is, every line after `` `define`` would be indented one extra level when...

Thanks for contributing! I've been trying to merge all (simple) syntax definitions into a table inside `plugin/verilog_systemverilog.vim`. After doing that you still need to include it in the `s:verilog_syntax_order` list...

Take into account that the syntax order is relevant, and may explain the folding issues. You were defining it after block, which made it have priority over it. Now it...

I think I already have a patch to end assign also with comma, but that alone will not solve this problem. I can try this later, but it is possible...

Hi @Strongsaxophone, You stepped on a syntax bug, which I never noticed before because I always separate the port name from the parentheses. The bad news is that my intention...