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Add reference to verilog-instance plugin in the README

Open antoinemadec opened this issue 6 years ago • 2 comments

Hi Vitor,

I just added this vim plugin: https://github.com/antoinemadec/vim-verilog-instance

This creates SystemVerilog port instantiation from port declaration. It is saving me a lot of time when I code in Verilog. I have been using it for years now and I just found the courage to add features, re write it and release it to the world.

I was wondering if you could add it to the "Other vim plugins for Verilog/SystemVerilog" section of verilog_systemverilog's README ? Also, feel free to report bugs or give me advice to make the plug-in clearer and cleaner.

Thanks in advance, Antoine

antoinemadec avatar Sep 26 '17 20:09 antoinemadec

Hi Antoine,

I have a Vim function that does something similar to what you accomplish with your plugin, although mine is much simpler and would not support multiple ports per line. I feel that my plugin should include this functionality, but I have not added my function because it is too simple. I intend to implement such functionality in the future, but I would like to have as following:

  1. Integrate somehow with SuperTab plugin such that when tab is pressed after a module name it would call an "instance completion" function.
  2. This "instance completion" function would then obtain the list of ports of that module from the tags file.

If you feel like implementing this functionality (in Vim Language, not Python please) then I would love to integrate that work into this plugin.

But because the functionality you are sharing in your plugin will eventually conflict with this plugin, I feel that it does not make sense to include such reference in the documentation.

Hope you understand my reasoning.

P.S. I've recently been a father, so please expect some delay in my updates.

vhda avatar Oct 04 '17 15:10 vhda

Hi Vitor,

First, congratulations on your baby :)

Then, regarding verilog-instance, I completely understand your reasoning. I agree that integrating it directly in verilog_systemverilog would be better. However here are some remarks/questions:

  1. Using the tags to automatically do it seems a great idea indeed. I think we should have 2 commands: one like verilog-instance, not based on tags and using vim motions (e.g.: gbi(); and the second using the tags to generate it, like "GetVerilogInstanceFromTags". That way people can use both depending on whether they generated the tags or not. What do you think ?

  2. I don't really like the idea of using SuperTab as a dependency for the GetVerilogInstanceFromTags feature. That could indeed interfere with YouCompleteMe, or other similar plugins. This feature should be as independent and orthogonal with other plugins as possible. What do you think ?

  3. I don't know vim-script very well, but what would be the advantages of using vim-script over python ? According to the tests I ran, the current python script of verilog-instance is fast enough (I ran it on a module with 300+ ports and tones of ugly comments). Python regex have the avantage of being powerful and easy to read.

In conclusion, I am going to keep verilog-instance alive until it is merged in verilog_systemverilog. In the mean time, I will be glad to help you integrate those features ! However I am starting a new job in 2 weeks and won't be very responsive in the next few weeks.

Cheers, Antoine

antoinemadec avatar Oct 04 '17 17:10 antoinemadec