Indent define blocks

[lewis6991]

Current:

`define macro_name(arg) \
always_comb begin \
    (arg) <= '0; \
end

Proposed:

`define macro_name(arg) \
    always_comb begin \
        (arg) <= '0; \
    end

[jeinstei]

I must admit to not being a fan of this by default. Would this be indented with reference to the current indent level, or only if not indented?

[vhda]

Such indentation could always be disabled using g:verilog_disable_indent_lst. All indentations are increments of the current level. That is, every line after `define would be indented one extra level when compared to the initial line, until the end of the `define.

[jeinstei]

Fair enough. Multi-line defines being indented makes sense. I misread the original intention.