verilog-perl
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veripool
Preprocessor doesn't handle one case of definition substitution properly
Author Name: Topa Tota Original Redmine Issue: 1659 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
If you run the preprocessor on this code
`define test(a1,a2) ((a1) + (a2))
`test val
( 1,2)
</code>
Output will be
((val 1) + (2))
</code>
It should give an error since there is no opening parenthesis after the definition name "test". However, what happens is that everything between the definition name and opening parenthesis gets prepended into the first argument.
This issue can mess up the code without the user detecting any errors. For example, user forgets to pass arguments to the definition name and a few lines later has a function call with same number of arguments.
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2020-01-10T11:52:59Z
Will fix this after next Verilator release. (Verilator has same preprocessor.)
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2020-01-11T14:16:44Z
Fixed in git towards eventual 3.472 release.
Also added to Verilator.