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Conditional event controls ("iff")
Author Name: Paul Donahue Original Redmine Issue: 1482 from https://www.veripool.org
Section 9.4.2.3 of IEEE 1800-2017 allows "iff" qualifiers on @ event controls. The example code in 9.4.2.3 is fairly straightforward:
module latch (output logic [31:0] y, input [31:0] a, input enable);
always @(a iff enable == 1)
y <= a; //latch is in transparent mode
endmodule
I'm currently using Verilator only for lint and I get this error on the above code: syntax error, unexpected iff, expecting ')' or ',' or or
The above code seems equivalent to the following which Verilator does support (at least for lint):
module latch (output logic [31:0] y, input [31:0] a, input enable);
always @(a) if (enable == 1)
y <= a; //latch is in transparent mode
endmodule
I also get lint errors when doing something similar in assertions:
assert property (@(posedge clk iff enable)
disable iff (reset)
(expr));
Can you introduce iff support? Thanks.
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-07-26T23:31:59Z
The event parsing needs some rewriting to handle this, but is relatively straight forward.
Added a disabled t_iff.v test as a placeholder.
This feature still seems to be missing. Are there any plans to support iff in events?
Perhaps you'd be willing to submit a pull to support it? (On the develop-v5 branch.)
I'd be interested in trying to make an attempt. If you have any starter tips (like where is event parsing done?) that would be awesome! If not, I'll maybe try looking on my own
@kbieganski checking to make sure you aren't already working on "iff"? Do you know what files might need updating to support it?
- Use develop-v5 branch as origin for the pull.
- [ ] Make test_regress style tests checking the expected behavior, confirm pass on another simulator.
- [ ] Add AstIff node type in AstNodeOther.h
- [ ] Improve verilog.y parser to "new AstIff" to handle the yIFF. Note the proper syntax should already be there, but commented out or with UNSUPPORTED error.
- [ ] Add code to V3Width to properly size it.
- [ ] Grep for places AstSenTree is used to see which need to be improved.
For event control expressions posedge a iff enable == 1 at least, I am not sure there is a need for a new AstIff node, just add the condition expression under the existing AstSenItem. V3SenExprBuilder on develop-v5 can be taught how to handle them, which might be all is needed (other than type checking in V3Width and thorough testing), but likely there will be more detail elsewhere.
I'm not working on this and not planning to, so you're good to go @sahilshahpatel (or anyone).
Do we have the support for "iff"?? Also am wondering if there is documentation for what SVA support is present in Verilator at the moment?
I haven't been working on this myself, just haven't had the time. If you want to, go ahead. If not, I still want to get to it eventually, just not sure when.
This is now supported, see: https://github.com/verilator/verilator/pull/4626
I'm getting failures on a similar construct:
some_label: assert property (disable iff(rst !== 1'b0) @(posedge clk) !(expr));
A pull request with the test, or if it is small you can just post the .v file that is needed in the issue itself.