vtr-verilog-to-routing
vtr-verilog-to-routing copied to clipboard
[Odin] How to trace the fail in odin.out file?
Hi,
The odin II process fails without generating any .blif file. In the Odin.out file, I am trying to trace back where the problem is. The output file looks like this:
usr/bin/env time -v /home/sun/vtr2/vtr/vtr_flow/../ODIN_II/odin_II -c odin_config.xml --adder_type default -U0 found pg block Preprocessing verilog. Adding power gating to module: top.Clock_divider+divider, net: sleep_signal Removing power gating signal from the module port definition list Found power gating block: top.pg_block+pg0 Command terminated by signal 11 Command being timed: "/home/sun/vtr2/vtr/vtr_flow/../ODIN_II/odin_II -c odin_config.xml --adder_type default -U0"
Could you give some advice on how to find this "signal 11"?
Thanks
Hi @Sun1927 - not sure if you have still this problem, but you can compile the Odin-II in debug mode by going into the "VTR_ROOT/ODIN_II" and then run "make debug". You would be able to run Odin-II in GDB by the following commands:
> gdb ./odin_II
> r -c {YOUR_ODIN_CONFIG_FILE}.xml
or
> r -V {YOUR_VERILOG_FILE} -a {YOUR_ARCH_FILE} {ADDITIONAL ARGUMENTS YOU NEED}
Then when Odin-II faces the segfault, you would be able to backtrace using the following commands:
> bt
or
> backtrace
If you would need further help, please provide us with your design files so we can go through the same process and find the issue.