XDC placement constraints support for interchange

[kboronski-ant]

Description

DEPENDS ON #1999 (I will rebase this branch to exclude commits from #1999 once it gets merged).

Parse XDC placement constraints using TCL interpreter.

• libtclcpp - C++ wrapper liblrary for TCL C API.
• xdc_constraints.h/cpp - create VprConstraints and modify netlist from a TCL script using XDC commands.

Supported commands:

• get_ports
  • by single name
  • by multiple names (multiarg call)
• set_property
  • PACKAGE_PIN (for single port)
  • IOSTANDARD (for any number of ports)

To read XDC files:

 --xdc_files <filename> ...

See https://github.com/antmicro/vtr-verilog-to-routing/pull/15 for another discussion about those changes.

About libtclcpp:

This is mostly header-based library for exposing C++ interfaces in TCL. Currently it allows "exporting methods from TclClient-derived classes as callable Tcl commands. A class needs to be added to an active TclContext (which represents the currently active interpreter) through TclCtx::add_client to register its methods. It also introduces a mechanism for wrapping C++ types in a generic way and imposing some compile-time type-safety when managing objects those types. Additionally it offers a C++ wrapper for typed and untyped Tcl lists (of course Tcl is a dynamically typed language, so typing restrictions apply only in C++ and are enforced through language constructs and extra runtime checks).

Caveats

Severe incompatibility with libsdcparse. Using timing constraints commands would require porting the interface for SDC commands from libsdcparse to libtclcpp. To handle more complex commands with optional arguments a Tcl argument parser would be useful. That's why at this moment only placement constraints are handled in this PR and SDC commands are not supported.

Another thing is that it works only for the interchange format at the moment. phys_grid_mapping field that was added to t_arch needs to be populated when loading an architecture definition and so far I've implemented it only for interchange. This field contains mappings from physical pins to grid locations so it shouldn't be hard to get that information when loading a VPR (XML) architecture definition.

Related Issue

#932

Motivation and Context

The current constrain system doesn't allow constraining IOs without knowing exactly what blocks are the going to be. It is also specific to VPR, while XDC seems to be a much more universal format.

How Has This Been Tested?

Manually constraining testarch IOs for LUT design from fpga-interchange-tests and checking results in GUI.

Types of changes

• [ ] Bug fix (change which fixes an issue)
• [x] New feature (change which adds functionality)
• [ ] Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

• [x] My change requires a change to the documentation
• [ ] I have updated the documentation accordingly
• [ ] I have added tests to cover my changes
• [ ] All new and existing tests passed