vtr-verilog-to-routing
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verilog-to-routing
Updating k6_N10_40nm.xml arch and adding a sparse version; making more user friendly for teaching use
Updating k6_N10_40nm.xml and adding k6_N10_sparse_crossbar_40nm.xml. These architectures are now more heavily commented and suitable for work in a grad course (ECE 1756).
Description
I cut the logic block areas to something more reasonable for a simple architecture like this; the area numbers for the logic blocks and the local mux delays for the sparse architecture are based on coarse scaling / guessing so they aren't extremely accurate.
Removed some very complex comments, and added some more basic ones. Deleted dead code and comments in the arch files. Switched to per LUT input delays so we can demonstrate flat routing.
Motivation and Context
Useful for teaching (assignment 4) in ECE 1756.
How Has This Been Tested?
Tested with simple MCNC designs to show they work and get reasonable results.
Checklist:
- [X] All new and existing tests passed
- [] Not done yet: should add a test to cover the sparse architecture.
@amin1377 : if you can take over updating golden results so we can land this it would be good. I don't know when I'll get back to it given the tasks in front of it ....
2024-08-16T14:26:26.5733988Z [32;1m14:26:26[0m | regression_tests/vtr_reg_strong/strong_clock_aliases...[Fail] 2024-08-16T14:26:26.5734837Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5736376Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc vpr_status Task value 'success' does not match golden '-1' 2024-08-16T14:26:26.5737824Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5739274Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc error Task value 'None' does not match golden '-1' 2024-08-16T14:26:26.5740587Z [32;1m14:26:26[0m | 2024-08-16T14:26:26.5741397Z [32;1m14:26:26[0m | regression_tests/vtr_reg_strong/strong_clock_aliases...[Fail] 2024-08-16T14:26:26.5742245Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5743787Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc vpr_status Task value 'success' does not match golden '-1' 2024-08-16T14:26:26.5745204Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5746651Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc error Task value 'None' does not match golden '-1' 2024-08-16T14:26:26.5748069Z [32;1m14:26:26[0m | 2024-08-16T14:26:26.5748824Z [32;1m14:26:26[0m | regression_tests/vtr_reg_strong/strong_clock_aliases...[Fail] 2024-08-16T14:26:26.5749676Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5751185Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc vpr_status Task value 'success' does not match golden '-1' 2024-08-16T14:26:26.5752678Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5754193Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc error Task value 'None' does not match golden '-1' 2024-08-16T14:26:26.5755554Z [32;1m14:26:26[0m | 2024-08-16T14:26:26.5756365Z [32;1m14:26:26[0m | regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay...[Fail] 2024-08-16T14:26:26.5757266Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5759228Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc logic_block_area_total relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 215576.0 2024-08-16T14:26:26.5761184Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5763325Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 107788.0 2024-08-16T14:26:26.5765393Z [32;1m14:26:26[0m | regression_tests/vtr_reg_strong/strong_clock_buf...[Pass] 2024-08-16T14:26:26.5766252Z [32;1m14:26:26[0m | 2024-08-16T14:26:26.5767066Z [32;1m14:26:26[0m | regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail] 2024-08-16T14:26:26.5767921Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5769899Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_total relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0 2024-08-16T14:26:26.5771721Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5773677Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0 2024-08-16T14:26:26.5775423Z [32;1m14:26:26[0m | 2024-08-16T14:26:26.5776187Z [32;1m14:26:26[0m | regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail] 2024-08-16T14:26:26.5777157Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5779099Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_total relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0 2024-08-16T14:26:26.5780853Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5782856Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 53894.0 2024-08-16T14:26:26.5784641Z [32;1m14:26:26[0m | 2024-08-16T14:26:26.5785407Z [32;1m14:26:26[0m | regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail] 2024-08-16T14:26:26.5786264Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5788137Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_total relative value 0.3339887945771287 outside of range [0.8,1.3] and not equal to golden value: 9108090.0 2024-08-16T14:26:26.5789862Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5791726Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 8353570.0 2024-08-16T14:26:26.5793471Z [32;1m14:26:26[0m | 2024-08-16T14:26:26.5794233Z [32;1m14:26:26[0m | regression_tests/vtr_reg_strong/strong_clock_modeling...[Fail] 2024-08-16T14:26:26.5795088Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5797061Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_total relative value 0.3339887945771287 outside of range [0.8,1.3] and not equal to golden value: 9108090.0 2024-08-16T14:26:26.5798793Z [32;1m14:26:26[0m | [Fail] 2024-08-16T14:26:26.5800677Z [32;1m14:26:26[0m | timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 logic_block_area_used relative value 0.33398894125505624 outside of range [0.8,1.3] and not equal to golden value: 8353570.0
Looks like we need to update golden (above from nightly_test_3). The clock aliases result is odd -- it seems the golden results don't expect success? If you can take a look at the clock_aliases test to make sure the new result is indeed a pass (flow completed) then we can just update golden for it too (not sure how we got a golden result that was failure).