vtr-verilog-to-routing
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verilog-to-routing
Improving automatic sizing algorithm
<Moving the discussion from email with @MohamedElgammal to a Github issue>
The auto-layout process increases device size to ensure that the design fits. It only compares the number of block locations of each type with the number of blocks in design with the same type and decides whether there are enough locations for all blocks. However, long chains in the design must be placed in consecutive locations, and the algorithm should take this into account and increase device size further if necessary.
Expected Behaviour
The device size should be further increased to make sure the design fits.
Current Behaviour
The device size is not large enough to place all of the blocks of a specific type, which results in an initial placement error.
Steps to Reproduce
These are the links to the design, architecture file, and config file for a design that produces the above error. Design Architecture file Config file Thanks to @aman26kbm for the design files.
Context
The issue was revealed while implementing improvement for initial placement.
