verilog topic
HDL-deflate
FPGA implementation of deflate (de)compress RFC 1950/1951
DDR2_Controller
DDR2 memory controller written in Verilog
FAST9-Accelerator
FAST-9 Accelerator for Corner Detection
edalize
An abstraction library for interfacing EDA tools
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
drec-fpga-intro
Materials for "Introduction to FPGA and Verilog" at MIPT DREC
SystemVerilogSHA256
SHA256 in (System-) Verilog / Open Source FPGA Miner
red-pitaya-notes
Notes on the Red Pitaya Open Source Instrument
awesome-hdl
Hardware Description Languages
FPGA_ThreeLevelStorage
【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。