pll topic
dpll
A collection of phase locked loop (PLL) related projects
avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperat...
eda-scripts
Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
iCEstick-hacks
iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Si5351mcu
Arduino Si5351 library tuned for size and click free.
Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
avsdpll_3v3
This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internshi...
FOC
sensorless fixed point foc use smo and pll in stm32
SOGI-PLL
Single-Phase PLL / Second-Order Generalized Integrators Phase Lock Loop