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Published 20 hours ago • verified publisher icon muhammadaldacher
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This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.

Analog IC design of high speed serial link transceiver for 10 GbaseKR standard using a 65 nm CMOS process

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard. The project consists of 4 main sections:

  1. Transmitter
  2. Receiver
  3. PLL
  4. CDR

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verified publisher icon muhammadaldacher

Metadata

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.

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