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Control and Status Register map generator for HDL projects

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Standalone OpenOCD and CMSIS-SVD based peripheral register viewer written on Python

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USB 2.0 FS Device controller IP core written in SystemVerilog

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Xilinx AXI VIP example of use

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🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)

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