TCal

@danc86 , I found my code and pushed it to the `dcache-count` branch on my fork of VexRiscv. The commit is here: https://github.com/tcal-x/VexRiscv/commit/067137d6f02d21646abe8d6968e57322dd8bbe7e . If you want to start building...

We might need to do an `apt install` of matplotlib if not using Conda.

`fmax-trials-fresh-build.yml` will still need the SiFive download since it doesn't use Conda.

In fact, having both the 8.3 SiFive toolchain and the litex-hub 10.1 toolchain causes link errors when building the software.

Hi @akku-t , we don't know of any problems using CFU Playground with the most recent release of Vivado, but we haven't tested it. If you want, I can assist...

``` 3402 fanout: net memdat_1[8] driver Cfu.filter_flow_restrictor.initial_VLO_Z:F ``` -- this seems to be providing `1'b0` i.e. constant zero i.e. GND. It's driven by an OXIDE_COMB with INIT = 32'h00000000.

I don't know the details yet about constant handling. I've dealt with it before on other FPGA architectures. One would think it's trivial, but it's not. Sometimes routing muxes or...

Here's some discussion relating to constant nets with FPGA interchange, between gatecat and litghost: https://github.com/YosysHQ/nextpnr/pull/591 And here's the current code related to packing constant nets for Nexus: https://github.com/YosysHQ/nextpnr/blob/master/nexus/pack.cc#L302-L321 And here's...

Hi @gits00 -- the immediate issue is that the FPGA (xc7a35t) doesn't have 0xfffff bytes of RAM resources. On Arty, the `main_ram` lives in the external DDR memory, and there's...

It might be worth deleting third_party/renode and rerunning ./scripts/setup to get the latest renode, just to eliminate that possibility.