TCal

Hi @bala122 , I've been trying to reproduce the issue myself and have not been successful (I have not seen either of the software upload issues). I'm am glad you...

Hi @vaughnbetz , what is the next step with this one? @jmah76 , thanks for all your work here!

:tada: thanks @jmah76 !

@jgoeders , @vaughnbetz , any comment? The concern is that the user finishes the build with no indication of any problems, and then the design does not run on the...

How wary are you of adding options? We could have an option `--fail-status-if-fail-timing` or something like that, that our wrapper would set, but wouldn't change default behavior.

> I'm sure that we had discussed this previously, but I can't find an existing issue.... @mithro there was a similar discussion regarding inconsistent treatment of timing failures in LiteX...

Since #2060 has been merged, I'll close this. We likely still have some work in F4PGA and CFU Playground to check the vtr result status and handle messaging correctly.

> Can we just change the CSR address? I'd discussed this a bit with Charles. He was wary of changing the address of the external interrupt mask, since although the...

(previous discussion: https://github.com/google/CFU-Playground/issues/596) Ok, here is the plan: 1) bump spinalHDL/vexriscv submodule in pythondata-cpu-vexriscv to get the workaround, and rebuild the CFU variants with the workaround (CFU.en is removed, i.e....

The first two steps above have been completed: 1. https://github.com/litex-hub/pythondata-cpu-vexriscv/pull/18. 2. https://github.com/google/CFU-Playground/pull/619