TCal

The `1110` and `1111` came from sign extension; but the actual code explicitly adds 0s, so that seems ok. So we're back to another thing to check that I mentioned...

I reproduced the unexpected behavior in SymbiFlow even with the explicit zero-extension: ``` wire signed [3:0] idx = {2'b00,i}; ``` If I instead use the following, I see the expected...

The README could be made more explicit by explaining what is done in `xc/xc7/tests/ddr/[scripts/]`, what is done in `build/xc/xc7/tests/ddr/`, and also, which `make` targets to run (`ddr_uart_arty_bit`, `ddr_uart_arty_prog`?). I tried...

Thanks for filing this! I had noticed this too. I hit this mostly when I have a small Python program on the host and want to paste it into the...

I had told @umarcor that I would take a look since I had just been playing with up-to-date Litex + Fomu.

Quick comments about the current litex\_boards targets/fomu.py that we're not bumping to: * It is now much more standardized with other LiteX targets * It seems it now only supports...

Thanks for the ping, @umarcor. The new fomu.py has been renamed kosagi_fomu.py. It would probably be confusing if we copied the old fomu.py into that directory, if that's what you...

Yes, it looks like a cut-and-paste error from line 48. @acomodi what do you think?

Hi @bala122; @aman26kbm and I were discussing a similar issue recently on [Gitter](https://gitter.im/CFU-Playground/community), please feel free to join the conversation there.

Hi @bala122 , thank you for clarifying. We delegate this part of the SoC design to Litex (the litex-boards repo specifically). If a board has external DRAM, then the SoC...