Taichi Ishitani

Hi @ms-ati , I consider the `dsl_eval` method an enhanced `instance_eval` method. Therefore, I think it is better that new instance variables will be copied to the `dsl` object. ```ruby...

Hi @ms-ati , Sorry for delay because I'm on year end/new year holidays. > You voted for instance variables written in the block being written to the DSL object. Your...

Hi @klevin92 , Thank you for opening PR! This uvm ral adapter is for AXI4-Lite and I think AX4-Lite does not support the narrow access feature. Do you need to...

> you will see only byte transactions disregard of your register's size Yes, I know. To do byte transactions, I set `supports_byte_enable` property of the uvm reg adapter. https://github.com/taichi-ishitani/tvip-axi/blob/c4a2013377a37eb58508b8637e5e44eca236c1e6/src/tvip_axi_ral_adapter.svh#L6 >...

> I will come back in a few days and bring a test case for this situation. Thanks but I already have a sample TB to execute built-in RAL sequences....

I think more modifications to the uvm reg adapter are needed to support AXI4 access so I create an issue #17 instead of this PR. Can you update #17 if...

Elab error below is reported. ``` ERROR: [VRFC 10-8792] cannot assign a string to an object of an unpacked type [/home/ishitani/workspace/rggen-sample-testbench/env/tvip-axi/src/tvip_axi_monitor_base.svh:375] ``` This error is caused by this code. https://github.com/taichi-ishitani/tvip-axi/blob/21a3bfc5f4137fa032b655b43f4ea83ae6f3b368/src/tvip_axi_monitor_base.svh#L375...

``` ERROR: [XSIM 43-3980] File "/home/ishitani/workspace/rggen-sample-testbench/env/tvip-axi/src/tvip_axi_monitor_base.svh" Line 58 : The SystemVerilog feature "ended" is not supported yet for simulation. ``` This `ended` method is a method of `tvip_axi_item` class but...

``` ERROR: [XSIM 43-3316] Signal SIGSEGV received. Printing stacktrace... [0] /lib64/libc.so.6(cfree+0x3c) [0x7fa328f015bc] [1] /storage/eda/tools/xilinx/Vivado/2022.1/lib/lnx64.o/libxsimverific.so(Verific::VeriIdRef::~VeriIdRef()+0x23) [0x7fa32a9c29e3] [2] /storage/eda/tools/xilinx/Vivado/2022.1/lib/lnx64.o/libxsimverific.so(Verific::VeriIdRef::~VeriIdRef()+0x9) [0x7fa32a9c2a09] [3] /storage/eda/tools/xilinx/Vivado/2022.1/lib/lnx64.o/libxsimverific.so(Verific::VeriAttributeSpec::~VeriAttributeSpec()+0x21) [0x7fa32aa92e71] [4] /storage/eda/tools/xilinx/Vivado/2022.1/lib/lnx64.o/libxsimverific.so(Verific::VeriAttributeInstance::~VeriAttributeInstance()+0x7e) [0x7fa32aa9a11e] [5] /storage/eda/tools/xilinx/Vivado/2022.1/lib/lnx64.o/libxsimverific.so(Verific::VeriAttributeInstance::~VeriAttributeInstance()+0x9) [0x7fa32aa9a199] [6] /storage/eda/tools/xilinx/Vivado/2022.1/lib/lnx64.o/libxsimverific.so(Verific::VeriNode::DeleteAttributes() const+0x53)...

It's seemed that xlab enters infinite loop when `foreach` constraints includes a range expression `[min:max]` which refer an object. For example: * https://github.com/taichi-ishitani/tvip-common/blob/eca5019ae925601cca94edf28432b63b74f3812e/src/tvip_common_macros.svh#L25 * https://github.com/taichi-ishitani/tvip-common/blob/eca5019ae925601cca94edf28432b63b74f3812e/src/tvip_common_macros.svh#L28