Taichi Ishitani
Taichi Ishitani
Check whether or not following tools support generated CSR modules/RAL packages. * Simulation * Cadence Xcelium * VHDL output * Mentor Questa/ModelSim * Aldec Riviera-PRO * GHDL * Synthesis *...
Currently, input values get from YAML file have no location info. For usability, get location info from YAML file and set them to input values.
Add Avalon-MM to supported host interface protocols. Specification is here. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
Add `internal` register type to support nested register block. This type is to specify a register block which is put within other register block. Outline of register map format: ```yaml...
Implement SystemRDL parser.
Signed-off-by: Taichi Ishitani Hi, I'm developing a code generator for CSR modules named RgGen. https://github.com/rggen/rggen This PR is to add sample CSR modules generated by RgGen to the tests.
Original issue is #16. The uvm reg adapter needs to support not only AXI4-Lite but also AXI4. To support AXI4, following changes are needed. * Set `bust size` and `bust...
Add fixed and wrapping burst support. To do this: * Update [slave data monitor](https://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_data_monitor.svh) * Update sequences * write and read sequences * update random constraint * slave default sequence...
I changed Module#attr_setter to adapt it to frozen-string-literal. This PR is to fix #286 .