Add ability to generate non-byte access by reg API

[klevin92]

This commit adds ability to generate non-byte write/read transactions on AXI interface while using UVM register API. Previously there were only byte transactions on the bus.

[taichi-ishitani]

Hi @klevin92 ,

Thank you for opening PR!

This uvm ral adapter is for AXI4-Lite and I think AX4-Lite does not support the narrow access feature. Do you need to support normal AXI or AXI5-Lite?

[klevin92]

HI @taichi-ishitani!

If I understood you correctly it's not narrow access. If you try to run uvm_reg_hw_reset_seq or any other build-in sequence you will see only byte transactions disregard of your register's size. Which isn't right if you have, let's say, 4-byte registers.

I will come back in a few days and bring a test case for this situation.

And answering your questions - yes, I need normal AXI4.

[taichi-ishitani]

you will see only byte transactions disregard of your register's size

Yes, I know. To do byte transactions, I set supports_byte_enable property of the uvm reg adapter. https://github.com/taichi-ishitani/tvip-axi/blob/c4a2013377a37eb58508b8637e5e44eca236c1e6/src/tvip_axi_ral_adapter.svh#L6

I need normal AXI4

OK, I understood. burst length also needs to be set to 1 to support normal AXI access.

[taichi-ishitani]

I will come back in a few days and bring a test case for this situation.

Thanks but I already have a sample TB to execute built-in RAL sequences. https://github.com/rggen/rggen-sample-testbench

[taichi-ishitani]

I think more modifications to the uvm reg adapter are needed to support AXI4 access so I create an issue #17 instead of this PR. Can you update #17 if you have more requirements and wait for me to implement that?