neorv32
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stnolting
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Hi, I’m success to build and flash fpga bitstream using LiteX and neorv32 core. I’m able to see the LiteX bios. I would like to run freertos application with this...
Runs in simulation, still has to be tested on hardware. More commits might follow. This pull request is just to let you know and avoid that we are both doing...
This is another PR in the series of subsets of #110 (#162, #163, #164, #165). `setups/osflow/Makefile` is replaced with doit tasks, plus some more elaborated Python code. Precisely, subdir `tasks`...
There are some (commercial) tools out there that have problems handling VHDL source files. Maybe it would be a nice feature to provide some kind of script that allows to...
@google provides some kind of framework with their [CFU-Playground](https://github.com/google/CFU-Playground) to add custom instructions to a RISC-V design. There is no real description of the interface, latency, et.c in their repo...
Most of the figures used in the documentation (mainly waveforms) are made with [WaveDrom](https://wavedrom.com/). It is possible to add those WaveDrom scripts right into the AsciiDoc source files of the...
Coming from #98. > https://github.com/stnolting/neorv32/pull/98#issuecomment-875487952 > > And one problem for me to work on is that I have not tested anything to do with the flash (in this case,...
Coming from #54 > https://github.com/stnolting/neorv32/pull/54#issuecomment-853920947 > By the way, what do you think about having the pre-build GCC toolchain as submodule inside this repository? Maybe in sw/gcc? > Tha scripts...
According to https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md, https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_application_image.vhd and https://github.com/stnolting/neorv32/blob/master/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/M/Makefile.include, currently each test program is compiled from assembler, an elf file is generated, then a bin file, which is then converted and replaced in...
We have discussed in several issues about adding a USB-UART peripheral to NEORV32 (either internal o external), which would allow to communicate the NEORV32 with a host laptop/workstation when using...