Shareef Jalloq

Results 19 issues of Shareef Jalloq

This is a first pass at the filelist backend. Still looking for feedback from the original discussion but thought a PR might kick start that. No test updates yet. See...

- added 'stdcell' arch option - added 'verilog' output format option - added 'tech_lib' option to specify .lib - updated Jinja templates

Hi there, I randomly noticed that when running fusesoc for Verilator that it uses all available CPUs for a parallel build. This seems to be due to the following lines...

I've been using the register model I created and having now added more tests to a single file, I noticed I'm getting warnings that more than one uvm_reg_block have been...

Hi, I know the SV support is a work in progress but I thought this syntax was interesting to note. ``` module module_name import module_name_pkg::*; `MODULE_NAME_PARAM_DECL ( ```

enhancement

Hi, I'm hitting a parse error that seems to come from YACC but it's no giving a very useful error message. I don't even know what file it is parsing...

question

It looks like the parser can't handle the final line of the module not having a newline. I'm getting parse errors such as: ``` Syntax error ERROR:VerilogModule::_ast: :125: before: /...

bug

The RDL spec shows how fields are packed in a register on p.44 of the v1.0 spec. In the case of LSB ordering, the following should hold: ``` lsb0; reg...

I had a quick look in the closed issues but couldn't see a matching title so forgive me if this has been reported already. I was just looking for a...

Just checked out HEAD and tried to run ./gradlew but get a build error. Seems to be a broken path to shadow.jar on github. [gradlew.log](https://github.com/Juniper/open-register-design-tool/files/3275549/gradlew.log)