Pyverilog SV parse error

SV parse error

Open sjalloq opened this issue 5 years ago • 2 comments

Hi,

I know the SV support is a work in progress but I thought this syntax was interesting to note.

module module_name import module_name_pkg::*; `MODULE_NAME_PARAM_DECL (

Jun 30 '20 12:06 sjalloq

SytemVerilog support is under development on feature_systemverilog branch. Stay tuned!

Nov 14 '20 03:11 shtaxxx

hi, Is the SV feature still under development now? Is there any rough schedule for releasing this feature?

Thanks & BR

Jan 25 '22 03:01 ruishihan