Shareef Jalloq

This update allows the user to specify an ASIC synthesis flow using a standard cell library using: ```yaml tools: yosys: arch: stdcell tech_lib: /some/path/to/your/std/cell/library/cell_name_tt_typical_max_1p50v_25c.lib output_format: verilog ``` I also noticed...

OK, think that does it from my side. I now know more about your pytest setup.

Hi, I might try and clean up the output formats at some point then but as you say, it's not that horrid. On your questions, for 1) the issue I...

@imphil @olofk, I was just about to ask some questions related to this as I'm looking at doing this for our project. Can we resurrect this thread. So far I've...

Here's my first pass which will hopefully stimulate some discussion: https://github.com/sjalloq/edalize/commit/08c07fd42df7a787c13196a900a6b52d7d9d1a85 It requires an update to FuseSoC too: https://github.com/sjalloq/fusesoc/commit/4db03432acddfcc4a0c4c605782f62afdf852f38

@olofk , is it possible to force `--no-export` from within a core file?

Happy to look at this again in the future when I have time but for now we're already using this backend.

I'm happy to look at it if you want to send me some pointers and don't mind when it's done.

I just wanted to add my voice to keeping FUSESOC_CORES. I've always used it to set the root for projects from with some sort of common sourceme. It also saves...

@Jbalkind, I need to look at how I wrote this again but I think your idea of an edalize backend might be more suitable. I'll try and take a look...