Pyverilog
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Parser error when no newline at end of file
It looks like the parser can't handle the final line of the module not having a newline. I'm getting parse errors such as:
Syntax error
ERROR:VerilogModule::_ast: :125: before: / while parsing /some/path/to/verilog.v
endmodule //modulename<nonewline>
Thanks! I can remove this bug by adding empty line to the imported text inside.