silabs-robin

Hi Mike. The issue is not resolved. It can be assigned to me, as I plan to look into it. edit: I see it is already assigned to me. Then...

1. The problem is in the central repo, yes. It manifested as an assertion error in simulation that couldn't be replicated in formal (so technically, the formal tool is possibly...

Relates to https://github.com/openhwgroup/core-v-verif/issues/1150 and https://github.com/openhwgroup/core-v-verif/issues/1188.

Should we stick to the [vplan review procedure](https://github.com/openhwgroup/core-v-verif/blob/master/docs/VerifPlans/VerificationPlanning101.md#verification-plan-reviews)? I.e. doing pre-reviews (like my annotated vplan above), and then hold a meeting to discuss all the feedback? I think some more...

Thanks for your diagram of the current implementation. It gave more insight into the situation. I think we have slightly different intentions for the use of the agent (apart from...

I ran ci_check for 40x using questa. So I think that should be this command: `./bin/ci_check -s vsim --core=cv32e40x`. The result I got was: ``` CI Check results: vsim-hello-world.log :...

The complete output is this: ``` [core-v-verif](326)> ./bin/ci_check -s vsim --core=cv32e40x -p ci_check: topdir : /work/ropeders/src/core-v-verif ci_check: core : cv32e40x ci_check: name_of_ci_check_regression : cv32e40x_ci_check_dev cd cv32e40x/sim/uvmt; make corev-dv CV_CORE=cv32e40x; make...

I looked a bit into it and I think I might have found where it goes wrong. (Though I don't yet have any concrete suggestions for how to fix it.)...

> are these assertions intented to be used for both formal and simulation? If so, which set of assumptions are required to use formal? No additional assumptions should be needed...

Just a small update on this: It was pending on some fixes in "cv32e40s/dev" which are now in, but also the vplan review meeting led to some vplan fixes that...