Ethan Sifferman

Convert severity tasks to Verilog

3

Hello! SystemVerilog added the system tasks `$fatal`, `$error`, `$warning`, and `$info` (20.10). However, sv2v does not convert them at all, causing Verilog tools to fail. It would be nice to...

Mutidimensional Packed Arrays Handler Does Not Match Commercial Synthesis Tools

1

Hello! When sv2v processes multidimensional arrays, the output differs compared to passing the SystemVerilog directly to commercial tools. Original SystemVerilog ```systemverilog logic [1:0][1:0] mem [2][2]; ``` Original SystemVerilog passed into...

Hello! In my opinion, if `unique` or `priority` statements are used on `case` statements, sv2v should add the attributes `parallel_case` and `full_case`, respectively. This is consistent with Vivado: From the...

Hello! ## Issue Commits https://github.com/openhwgroup/cvfpu/commit/51e6ba8739bc6df720a493b1a23e6e6d2a9f512a and https://github.com/openhwgroup/cvfpu/commit/1548daed714f94f32dc8401aa0587bda8ad1034c from PR https://github.com/openhwgroup/cvfpu/pull/102 have introduced a bug due to the use of `NUM_INP_REGS-1` without checking `NUM_INP_REGS > 0`. This causes the [basic instantiation...

Fixes https://github.com/verilator/verilator/issues/5070 (I still need to add a couple tests, but I'm posting the PR now in case you have early suggestions). Changes: * A `z` or `x` in a...

`$readmemb` and `+verilator+rand+reset` incompatible

1

Hello. I discovered that `+verilator+rand+reset` will change the `x` values in `$readmemb` files to hex digits instead of binary digits. I would be happy to look into this in the...

Should use CVXIF

```systemverilog module MultiDimHierPath9 ( input logic [3:0] a, input logic [3:0] b, output logic [1:0][3:0] out ); typedef logic [3:0] logic4; function automatic logic4 [1:0] f(logic4 a, logic4 b); logic4...