Convert severity tasks to Verilog

[sifferman]

Hello!

SystemVerilog added the system tasks $fatal, $error, $warning, and $info (20.10). However, sv2v does not convert them at all, causing Verilog tools to fail. It would be nice to convert them into Verilog-2005 tasks so that they can still be used in pure Verilog tools.

This is my interpretation of the LRM:

• $error, $warning, and $info should all be turned into $display.
• $fatal should first run a $display, then run $finish

This is a description of what should go in the $display:

[Each task should include a tool-specific message with] the following information:

• The file name and line number of the severity system task call. The file name and line number shall be the same as `__FILE__ and `__LINE__ compiler directives, respectively.
• The hierarchical name of the scope in which the severity system task call is made.
• For simulation tools, the simulation run time at which the severity system task is called. The tool-specific message shall include the user-defined message if specified.

It could be helpful to have `__FILE__ and `__LINE__ for both the inputted .sv file and the outputted .v file. Verilog-2005 has no `__FILE__ equivalent, but it does have `line (19.7).

I would be happy to look into this if you'd like. :)