Ethan Sifferman

```systemverilog module MultiDimHierPath8 ( input logic [3:0] a, input logic [3:0] b, output logic [1:0][3:0] out ); typedef logic [3:0] logic4; struct packed { logic4 [2:0] vector3x4; } s; assign...

Found an issue with [alaindargelas/synlig@stable_rs](https://github.com/alaindargelas/synlig/tree/stable_rs) ```systemverilog module MultiDimHierPath7 ( input logic [3:0] a, input logic [3:0] b, output logic [1:0][3:0] out ); struct packed { logic [1:0] unused1; logic [1:0][3:0]...