Schuyler Eldridge

Logging approval from @azidar via offline discussion.

> Why try to fix what is not broken and create extra work by requiring parsers to track types in order to disambiguate between SubAccess ([...]) and Bits (after this...

This is an insufficiently specified area. 😅 Yes, the ABI version needs to also be specified. The ABI also needs to be specified on external modules as that represents something...

> Not sure where to ask this, but is ABIv2 expected to match the behavior of firtool --preserve-aggregate=all --scalarize-top-module=false ? Yes. Though, ~this is a very untested path~ this path...

Making the defname take a string makes sense to me. The current identifier approach is fine for referencing the results of other FIRRTL compilations, but, as you mention, doesn't work...

@darthscsi or @dtzSiFive, WDYT?

Possibly or possibly this becomes the "verification" section of the spec. @mmaloney-sf had already identified that many of the "commands" (https://github.com/chipsalliance/firrtl-spec/blob/dcd63187d99a923b67caec597e374b8e400f070b/spec.md#commands) are all really verification-only operations. Extending this to support...

My high level understanding of that commit is that it will add intermediate variables for situations where there are multiple sinks of a vertex: https://github.com/verilator/verilator/commit/5e1fc6e24d9c2706d9871de9bec25cebf2a95ac7#diff-b97010442f078f1560701a463b217dcdb608556f4e3757d896256fe1e440034cR83 However, here the variable and...

More archaeology, it looks like there was a related bug which was partially fixed with: https://github.com/verilator/verilator/pull/4942 The fix may be a similar thing where `isForceable` is queried to short circuit...

Yes, they should be mutually exclusive as HTIF argument parsing happens after `emulator.cc` argument parsing. The PlusArg PR (freechipsproject/rocket-chip#1192) effectively only generates your plusarg struct and the help text based...