Schuyler Eldridge

If you want specification FIRRTL, this will need some work on the CIRCT side. CIRCT has an exporter of FIRRTL dialect, but it's a bit out of date. It can't...

Fair point. The best documentation for this is the API docs: https://javadoc.io/doc/org.chipsalliance/chisel_2.13/latest/circt/stage/ChiselStage$.html

While LowerToHW shouldn't fail, it is also unexpected to see an invalid value at LowerToHW. This should have been converted to a special constant zero during SFCCompat, but it was...

If not hard dropping this, moving the tests of the parsing of this into a feature-gated test would be good.

You're correct in that this is not aligning with the spec. We keep discussing an alternative to this, and changing the spec to align with it, of a "manifest" which...

See https://github.com/chipsalliance/firrtl-spec/issues/189 for ideas around FIRRTL manifests.

Because I saw SCC fly by, this is a draft PR that implements group traits for FIRRTL connections: https://github.com/llvm/circt/pull/6491 I'm not convinced that this is fully working yet, as the...

Generally, having end-to-end integration tests that are checking the legality of the emitted Verilog are great. This was a huge missing testing mode that would have helped early on when...

> Having Chisel emit "ABI" files directly itself for this use case is a pain. I actually think this is the correct approach. It is always allowable for a user...

I kicked off a bunch of Windows builds off of `main` and they all passed. So, this at least appears to be deterministically passing (as it seemed to be deterministically...