Schuyler Eldridge

The issue with `ComponentName` always being converted to `ReferenceTarget` can be resolved with a strategy like https://github.com/freechipsproject/firrtl/pull/1311 where `ReferenceTarget`s are converted to `InstanceTarget`s.

I can see a need for a ` DependencyManager` where the `prerequisites` are derived from the `targets` directly as opposed to being set by `currentState`. This makes a lot of...

I think this notion of a transform as solving a `DependencyManager` sub-problem makes sense. The `DependencyManager` is recursively solving sub-problems to handle re-lowering. It's natural that users would want to...

@albertchen-sifive: Sorry this has been stalled. it seems to make sense to me to generally move optimizations that happen late, currently, up to high FIRRTL. This will make some things...

This looks great! I rebased #1220 on this and this gets `AsyncResetSpec` passing (one other test is failing, but that looks spurious). If vector collapsing is considered an optimization transform...

Also, note that this is intended to _not_ conflict with a future syntax for parameters or type parameters which would look similar, but would be located after the module name...

> Do instances need to specify this? They do not. It would also create some complications if they did as a single public module could then have different conventions requiring...

@rwy7: FYI, give this some thought about composition with true Verilog width parameterization.

After some discussion with @rwy7, `option` seems like a better name to describe what is going on. I'll revise this and get this moving.

This one has users and, after talking with @dtzSiFive, it would be better to hold off on this for 4.0.0 so we can figure out how to get Chisel to...