Schuyler Eldridge

I'd suggest moving this to a slightly different model based off of how I've gotten CIRCT CI/CD working for downstream projects, e.g., Chisel: 1. There is a permanent "staging branch"...

I think this makes sense---have `ExportVerilog` ignore ops outside HW modules that it doesn't understand. We're already kind of in this situation with OM dialect, though `ExportVerilog` is aware of...

That error looks to be using a pretty old message. However, I think it's saying that the target specified by the annotation doesn't exist. E.g., inside `circuit TestHarness`, inside `module...

This looks like a situation where the annotation file is from Chisel and the FIRRTL has been run through SFC to the point of lowering types. That should produce an...

@ekiwi-sifive: We're on the same page---that's exactly what I was thinking. Intentionally invalidate the prerequisites and see if not having them causes the transform to error or produce different output....

Does this need to pay attention to the source locators?

From the dev meeting: We can see if simply relaxing `CheckResets` will work. However, this should be tested that it works with both `-X verilog` and `-X mverilog`.

I'm in agreement that annotations should have no effect on duplication. However, I agree with @azidar that these need to be renamed to `InstanceTarget`s. tl;dr: hierarchy mainpulations (e.g., `DedupModules`, `EliminateTargetPaths`)...

@azidar can correct me, but `Target` cannot be used to point to a sub*access*. (I incorrectly wrote the name of that test as a subindex, but it's actually a subaccess.)...

Nah, I think it's fine. Really a `ComponentName` pointing at a subaccess doesn't make sense either, it's just that this happens to work for wiring because you can cram an...