Schuyler Eldridge

You don't have `riscv-linux-gcc` on your path. You need to install the _linux_ version of the RISC-V toolchain first. In `riscv-tools` this is not handled automatically by the `build.sh` script....

I think there's a broader problem of the interpreter having `x`'s in simulation. I got bit by this today due x-optimism. Both Treadle and the Verilator backends are doing the...

If possible, is prefer to have this as a website update.

@edwardcwang: Maybe there's a better way to put it, but I think @chick was asking for a counterpart to the ["Get me Verilog" website/wiki FAQ](https://www.chisel-lang.org/chisel3/faqs.html#get-me-verilog) with answer: ``` scala object...

Try installing `graphviz` for your distribution which provides the `dot` program.

As a workaround for Windows, is the hosted Binder instance sufficient for your use case? https://mybinder.org/v2/gh/freechipsproject/chisel-bootcamp/master

That's a good point. Gating (by default) Verilog generation on tests having passed would be safer. However, I think it's an anti-pattern to go diving through `test_run_dir` to find the...

The thought occurred to me about having the submodule. However, I'm really of the opinion that we should coalesce around one source of information for new users. This does put...

Re: mill... As far as I could dig up: no. This also appears to have been punted on internally: - https://github.com/lihaoyi/mill/issues/134 Granted, there's technically nothing too interesting that g8 is...

This went through a deprecation schedule. - This was deprecated in `firtool-1.57.0`: https://github.com/llvm/circt/pull/6188 - This option was removed in `firtool-1.60.0`: https://github.com/llvm/circt/pull/6191 The error message that you get for this tells...