Schuyler Eldridge

The SystemVerilog output should be fine for all backend tools. If you need more control, you can use some of the LoweringOptions here, likely, enabling `disallowLocalVariables` to avoid `automatic logic`....

`DataMirror.internal.chiselTypeClone` or `chiselTypeOf` do the expected thing here for both `Probe` and `Const` modifiers. So, maybe this is a "working as intended"? Do you recall why `chiselTypeOf` has the restriction...

The FIRRTL perspective, which I think is the new Chisel perspective, is that direction is _not_ part of the type nor is it a modifier. It's a bit associated with...

There are some hints of this in Chisel 6 and beyond. Something like this will happen. However, it is not expected to be where Scala generator-time parameters are automatically translated...

What would an explicit `Aligned` do? Isn't that a no-op?

Nice find, and thanks for working with the Verilator folks on getting this tracked down. > I think few people are using SInt in Chisel. But it should be correct....

Sorry, I forgot about this. I reduced this just now to: https://github.com/llvm/circt/issues/6961 @dtzSiFive identified that there was a very similar bug related to arithmetic shift right which was fixed by...

For completeness, the output of the erroneous example will now produce: ``` verilog // Generated by CIRCT firtool-1.73.0-56-g3ef492c80-dirty module Test1( input clock, reset, input [15:0] io_in0, io_in1, io_in2, output [15:0]...

@mwachs5 wrote: > What is the error? Edited it into the issue text at the bottom.

A user can do `Module(new RawModule{})` today which is odd, but allowable. Maybe the extra safeguard against this is helpful? If we're really trying to guard against module creation with...