sara_mahmoudi

Dense initial placement

4

Initial placement used to fail in case of high utilization or long chains. New approach called dense_placement has been added to initial placement, make it possible to redo initial placement...

The auto-layout process increases device size to ensure that the design fits. It only compares the number of block locations of each type with the number of blocks in design...

Support 3D Custom Switch Blocks

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#### Description This pull request support 3d custom switch blocks in the architecture file and automatically add the inter-die edges between tracks in different layer to RR graph. #### Types...

6D router lookahead and 3D custom switch block conflicts

4

My branch (3d_track_to_track_conn) is working with 6d_router_lookahead for 3D custom switchblocks. The last commit id from 6D_router_lookahead that I merged with my branch is "c3a247092cf66167c4eb3b0c7d91fefecabb1fb2". Up to this commit, an...

Treating clock as global nets will make net_delay zero. Using two-stage router, the delay of an interconnect is calculated by adding 'driver delay', 'cluster net delay' and 'sink delay', which...

Using Tileable RR graph, each wire can have different ptc numbers (instead of only one). We are supporting this feature using node_twist_ data structure. However, we keep a single twist...

Pass actual fc instead of fc_max to connect to pins

7

#### Description This PR addresses the issue mentioned in [Issue #2641](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/2641). #### Motivation and Context #### How Has This Been Tested? I tested the branch with my examples with fc_override...

Specify a single location or a specific region for a custom switch block

2

This PR generalize the custom switch block description to allow the user to specify a exact (x,y) location for the switch block by setting type="XY_SPECIFIED", the exact syntax is explained...

Passing only Fc max to pin to track map function

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#### Current Behaviour While we want to create connection blocks (pin->track and track->pin connections), we first loop over segments and calculate the maximum Fc over all pins of one block...