vtr-verilog-to-routing
vtr-verilog-to-routing copied to clipboard
verilog-to-routing
Flat router delays in timing report are inaccurate due to treating clock as global net
Treating clock as global nets will make net_delay zero. Using two-stage router, the delay of an interconnect is calculated by adding 'driver delay', 'cluster net delay' and 'sink delay', which driver and sink delays are intra-cluster delay between source pin to cluster pin and cluster pin to sink pin. However, flat router uses atom net and it is from one primitive to another, which means we don't need to add 'driver delay' and 'sink delay' anymore and we simply use net_delay for it.
Current Behaviour
The following attach screenshot shows the difference between timing reports in two-stage (left side) router and flat router (right side). timing_report_screenshot We can see in two-stage router we have intra 'io' routing is calculated (0.042) correctly based on architecture file and the same delay in flat router reported as 0 since net_delay is 0 as it is a clock.
Expected Behaviour
intra 'io' routing should be considered in flat router scenario, as well.
Steps to Reproduce
- Clone and build master branch
- Architecture file: vtr_flow/arch/timing/k6_frac_N10_40nm.xml, Design file: vtr_flow/benchmarks/blif/clma.blif
Context
@tpagarani @amin1377 @vaughnbetz
