Support for SystemVerilog compilation using sail -sv

[torjeikenes]

Hi I am wondering if there is a plan to support compilation of the model to SystemVerilog using the -sv flag from sail.

I have attempted extending the makefile with this command: sail -sv $(SAIL_SRCS) model/main.sail -sv_output_dir generated_definitions/sv

But I get the following error: Fatal error: exception Invalid_argument("List.init")

I am curious if there is ongoing work to support this and/or if anyone knows how much effort it might take to get this working?

[Timmmm]

The SystemVerilog support is very experimental. I really doubt it would work with the whole RISC-V model. I think the thing you've hit is that it doesn't support lists.

IIRC I had a play around with it and it also doesn't support loops (I think it even silently miscompiled them).

So yeah it's going to be a lot of work! Definitely an eventual goal though.

[Alasdair]

I have a branch where this works, but it's a bit out-dated

[torjeikenes]

@Alasdair, Is it public? That would be interesting to have a look at.

[kourzanov]

+1 here. is there a version that works?

[rsnikhil]

I'd imagine compiling to full SystemVerilog, for simulation only, should not be too difficult; it would likely be difficult to compile to synthesizable SV?

[Alasdair]

The current implementation is very much a prototype. I've been re-working it recently, but that version is not quite in a usable state.

The SystemVerilog it generates is purely Combinational Logic, so it should be synthesizable provided you avoid things like lists and strings.

[ludwigatlubis]

We (LUBIS EDA) could really use such a generation even if it is combinational. Is there any chance we can jointly work on this?