cheshire
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A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
* Add write support for SD cards, improve timeout * Add `ebreak` in boot ROM so programs loaded using GDB yield on completion. * Add a baremetal program for bootable...
very drafty :-) no yet complete in any way
PR #91 added a USB controller. This results in the following errors messages during/after Linux boot: ``` [ 100.612980] usb usb1-port4: Cannot enable. Maybe the USB cable is bad? [...
Hi, I want to make interrupt handler from external interrupt(intr_ext_i port) in Cheshire. Which part should I change?? I wrote the trap_handler() function (generate "Intr" via UART) in hello_world.c and...
To do: - [x] Add DRAMSys. - [x] Update DRAMSys ref once https://github.com/pulp-platform/dram_rtl_sim/pull/4 and https://github.com/pulp-platform/dram_rtl_sim/pull/5 have been merged and released.
According to https://pulp-platform.github.io/cheshire/tg/xilinx/, it is written that we can use Vivado => 2020.2. Maybe we could add a quick note about how to call the correct version ? https://github.com/pulp-platform/cheshire/blob/0deceeef2a91c5d5d3e4d1aa8ef3fa439e97d5d4/target/xilinx/xilinx.mk#L10 ```...
Optionally use Hyperram instead of DDR3 on Genesys2. ToDo: - [x] Integrate Hyperram - [x] Add constraints - [ ] Streamline switching between DDR3 and Hyperram (add another target?)