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AXI4 on chip memory slave

2

This PR adds the `axi_to_mem` module to translate AXI4 to a simple memory protocol. This PR partially replaces #115 and #213.

micprog

colluca

This PR adds a banked variant of `axi_to_mem` for higher throughput. This PR also adds a test for `axi_to_mem_banked`, which also tests `axi_to_mem` as it is called within the new...

micprog

thommythomaso

I am trying to use this IP with FuseSoc and everything seems to be working. However, I want to use `axi_driver` in `axi_test` package in my test bench but it...

hossein1387

In the [section on EDA tools](https://github.com/pulp-platform/axi#which-eda-tools-are-supported) you could add a suggestion for developers with access to EDA vendor support to report issues with SystemVerilog language support. Open source projects are...

jeras

AXI4 on chip memory slave

1

Rebase of the relevant changes in #115 on the current master This adds two modules: - `axi_to_mem`: Slave module, max throughout simultaneous read/writes 50%, read or write 100%. - `axi_to_mem_banked`:...

micprog

Running testbenches with Verilator or Vivado

3

I would appreciate some info on how to build the testbenches using Vivado or verilator. It's not straightforward how to use the CI flow based on Quartus as a reference...

vkomenda

about the full_o of IDcounter

1

Regarding the full_o of IDcounter, why is full_o set to 1 when the count value of any ID is full, and the counter no longer counts，what is the reason for...

hdu-lpl

Combinatorial path from valid to ready

6

Edit by @accuminium: You may want to jump to the [description of the situation and the solution](https://github.com/pulp-platform/axi/issues/195#issuecomment-1008765533). Original post below: --- https://github.com/pulp-platform/axi/blob/5380c5fc99aed848d59d0fd8867e461c7b24fd4d/src/axi_dw_downsizer.sv#L729 Hi Folks, an above link tells that, it...

Realhssuperman