podgori

Generic TDD Engine

2

Replaces the existing axi_tdd with the new version

## PR Description This PR fixes some issues which were found in simulation: 1. Synchronizes the AXI AD9361 transmission path with the TDD output synchronization signal. 2. Sets initial values...

## PR Description Added documentation for the Data Offload IP. Removed the existing (now duplicated) documentation from library/data_offload. ## PR Type - [ ] Bug fix (change that fixes an...

DMA Generic Transfer Start Synchronization

3

## PR Description This PR adds a generic **sync** port used for transfer start synchronization. The signal used for synchronization is assumed to be synchronous with the interface clock which...