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Published 20 hours ago • verified publisher icon analogdevicesinc

Generic TDD Engine

Open podgori opened this issue 2 years ago • 2 comments

Replaces the existing axi_tdd with the new version

podgori avatar Jul 26 '22 13:07 podgori

The Guideline checker action for this PR will fail because SystemVerilog files are not fully supported, for example packages.

IuliaCMoldovan avatar Jul 26 '22 13:07 IuliaCMoldovan

v1.1: Minor update in axi_tdd_channel.sv to change the reset value of ch_pol to DEFAULT_POLARITY.

podgori avatar Aug 17 '22 13:08 podgori

V2

  • Removed tdd_active output
  • Replaced .xdc constraints file with .ttcl constraint generating file
  • Fixed ch_pol to reset to DEFAULT_POLARITY
  • Renamed CDC sync flops for ext sync signal

podgori avatar Oct 06 '22 09:10 podgori

v2.1: Added the TDD regmap files.

podgori avatar Oct 11 '22 08:10 podgori

v2.2: Integrated the new TDD engine in the ad9081_fmca_ebz_x_band project.

podgori avatar Nov 21 '22 19:11 podgori

v2.3: Updated the scripts to create a wrapper around the TDD core and generated channel slices.

podgori avatar Dec 06 '22 11:12 podgori