DMA Generic Transfer Start Synchronization

[podgori]

PR Description

This PR adds a generic sync port used for transfer start synchronization. The signal used for synchronization is assumed to be synchronous with the interface clock which needs to be triggered by the sync signal.

On the receive AXI Streaming interface, the user can choose to receive the synchronization signal on TUSER instead of 'sync', which is the default setting, configurable through the AXIS_TUSER_SYNC synthesis parameter.

The fifo_wr interface has the SYNC signal removed, since it is now a generic synchronization port, applicable to all interfaces. Therefore, all affected IPs and Projects had to be updated to address this change.

Tested this change in simulation. Please refer to: https://github.com/analogdevicesinc/testbenches/tree/pluto_phaser_tx_sync

PR Type

• [ ] Bug fix (change that fixes an issue)
• [x] New feature (change that adds new functionality)
• [ ] Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• [x] I have followed the code style guidelines
• [x] I have performed a self-review of changes
• [ ] I have compiled all hdl projects and libraries affected by this PR
• [ ] I have tested in hardware affected projects, at least on relevant boards
• [x] I have commented my code, at least hard-to-understand parts
• [x] I have signed off all commits from this PR
• [x] I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• [x] I have not introduced new Warnings/Critical Warnings on compilation
• [x] I have added new hdl testbenches or updated existing ones